Data processing system having an external device interface with assigned addressing

ABSTRACT

A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a microprocessor and, moreparticularly, to improvements in the external bus interface of amicroprocessor.

[0002] There are microprocessors (micro-controllers) equipped with anexternal bus capable of being directly connected to varioussemiconductor memories including a synchronous DRAM (dynamic randomaccess memory). Such microprocessors are discussed illustratively inNikkei Electronics published by Nikkei-MacGrow-Hill, Inc. (Feb. 14,1994, pp. 79-91).

[0003] So-called PC cards such as memory cards and I/O cards are now inwidespread use. The conditions for interfacing the PC cards tomicroprocessors and the like have been standardized by the JapanElectronics Industry Development Association (JEIDA) and the PersonalComputer Memory Card International Association (PCMCIA). The PC cardinterface includes the IC memory card and I/O card interface provisionsfor the 68-pin type, stipulated in “6. Electrical InterfaceSpecifications” of the Guideline Ver. 4.1. The PC card interface isimplemented illustratively by use of a dedicated integrated circuit (IC)chip such as the 82365SL.

SUMMARY OF THE INVENTION

[0004] In conventional microprocessors, the bus for coupling to PC cardsis furnished independently of the bus for connecting semiconductormemories. Furthermore, the PC cards are connected to the bus via thededicated IC chip which controls the PC card interface. This entails acomplicated bus constitution and an increasing number of design stepsrequired where the PC card interface is to be incorporated in personalcomputers and portable data processing terminals. With more parts to beattached externally to the microprocessor because of the PC cardinterface, it takes more time to develop personal computers and portabledata processing terminals. The prolonged period of product developmenthampers these products from being reduced in manufacturing costs.

[0005] It is therefore an object of the present invention to provide amicroprocessor that is easy and convenient to use. Another object of theinvention is to provide a microprocessor which, when incorporated in apersonal computer or like product equipped with the PC card interface,allows the computer to be designed in a reduced time and with fewerparts to be attached externally thereto, whereby the manufacturing costof the computer as a whole is reduced.

[0006] These and other objects, features and advantages of the inventionwill become more apparent upon a reading of the following descriptionand appended drawings.

[0007] The invention disclosed in this specification is outlined asfollows: according to one aspect of the invention, there is provided amicroprocessor to be incorporated in a personal computer, a portabledata processing terminal or the like, the microprocessor being furnishedwith a bus state controller. The bus state controller BSC, connected toan external bus, controls parallelly the interfaces for varioussemiconductor memories such as a ROM, a burst ROM an SRAM, a PSRAM, aDRAM and a synchronous DRAM, as well as for PC cards such as a memorycard and an I/O card. The bus state controller BSC includes a controlregister (PCR) for controlling the time to set up PC card start signals(−OE, −WE) where a synchronous DRAM is connected.

[0008] Preferably, the inventive microprocessor has the address space ofthe external bus divided into a predetermined number of areas to whichvarious semiconductor memories and PC cards are fixedly assigned. Theaddress space areas are assigned independently two kinds of physicaladdresses: those in effect when the I/O card functions as an I/O device,and those used when the I/O card acts as a memory. The microprocessor ispreferably equipped with a memory management unit for converting aninternal logical address to a physical address applicable to theexternal bus.

[0009] The foregoing objects are attained through the use of theabove-outlined means for the following reasons: the inventivemicroprocessor is free of constraints of physical address assignmentsand requires fewer parts to be attached externally thereto for interfacecontrol. As such, the microprocessor has various semiconductor memoriesand PC cards such as a memory card and an I/O card connected directlyand concurrently to a bus external to the microprocessor. Consequently,the microprocessor becomes more convenient to use. When incorporated ina personal computer equipped with PC card interfaces, the microprocessorhelps reduce the number of steps to design the computer. With itsexternally attached parts reduced in quantity, the microprocessor costsless to manufacture.

[0010] The bus state controller BSC has the control register (PCR) forcontrolling the time to set up PC card start signals (−OE, −WE) wherethe synchronous DRAM is connected. The control register arrangementmakes it possible to control the fall of a clock signal CKIO for anoutput enable signal (−OE) and a write enable signal (−WE) used as thePC card start signals, and to control the time to set up addresssignals. As a result, even if a PC card and a synchronous DRAM areconnected concurrently to the inventive microprocessor MPU, themicroprocessor may access both the PC card and the DRAM with nodifficulty.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a system block diagram of a personal computer includinga microprocessor practiced as an embodiment of the invention;

[0012] FIGS. 2(A), 2(B) and 2(C) are external views of the personalcomputer shown in FIG. 1;

[0013]FIG. 3 is a block diagram of the embodiment included in thepersonal computer of FIG. 1;

[0014]FIG. 4 is a substrate layout view of the embodiment in FIG. 3;

[0015]FIG. 5 is an address map showing a typical address space of a busexternal to the embodiment of FIG. 3;

[0016]FIG. 6 is an address map showing address space areas 5 and 6 ofthe external bus for-the embodiment of FIG. 3;

[0017]FIG. 7 is a connection diagram partially showing typicalconnections of the external bus to the embodiment of FIG. 3;

[0018]FIG. 8 is another connection diagram partially showing typicalconnections of the external bus to the embodiment of FIG. 3;

[0019]FIG. 9 is an interface block diagram of an interface example inwhich a PC card is connected to the external bus shown in FIGS. 7 and 8;

[0020]FIG. 10 is a partial table of typical signals used on the externalbus shown in FIGS. 7 and 8;

[0021]FIG. 11 is another partial table of typical signals used on theexternal bus shown FIGS. 7 and 8;

[0022]FIG. 12 is a block diagram of a bus state controller included inthe microprocessor of FIG. 3;

[0023]FIG. 13 is a state transition diagram applicable to the bus statecontroller of FIG. 12;

[0024]FIG. 14 is a table of typical states applicable to the states ofthe bus state controller shown in FIG. 13;

[0025]FIG. 15 is a table of typical transition conditions for the busstate controller of FIG. 13;

[0026]FIG. 16 is a signal waveform view showing typical signal waveformsin effect when the memory card is accessed by the microprocessor of FIG.3 not entailing wait state;

[0027]FIG. 17 is a signal waveform view showing typical signal waveformsin effect when the memory card is accessed by the microprocessor of FIG.3 entailing wait state;

[0028]FIG. 18 is a signal waveform view showing typical signal waveformsin effect when the memory card is accessed by the microprocessor of FIG.3 in burst mode;

[0029]FIG. 19 is a signal waveform view showing typical signal waveformsin effect when the I/O card is accessed by the microprocessor of FIG. 3not entailing wait state;

[0030]FIG. 20 is a signal waveform view showing typical signal waveformsin effect when the I/O card is accessed by the microprocessor of FIG. 3entailing wait state;

[0031]FIG. 21 is an interface block diagram partially depicting anexample in which a PC card and synchronous DRAMs are connected to themicroprocessor of FIG. 3;

[0032]FIG. 22 is a signal waveform view showing typical signal waveformsin effect when a synchronous DRAM is accessed; and

[0033]FIG. 23 is a block diagram of a typical synchronous DRAM.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034]FIG. 1 is a system block diagram of a personal computer includinga microprocessor MPU practiced as one preferred embodiment of theinvention. In FIG. 1, one of the basic components of the personalcomputer is a mother board MBD incorporating the microprocessor MPU. TwoPC cards, illustratively a memory card MEMC and an I/O card IOC, areconnected to the mother board MEMC through PC card slots PCSL1 andPCSL2, respectively. A liquid crystal display LCD and a keyboard KBDconstituting a man-machine interface are connected via connectors LCDCONand KBDCON respectively to the mother board MBD. The memory card MEMCmay be composed of an SRAM (static RAM), an EPROM (electricallyprogrammable read only memory), an EEPROM (electrically erasableprogrammable read only memory) or a flash EEPROM. The I/O card IOC maybe made up of a modem for facsimile transmission and data transfer, acontrol circuit for use with a LAN, a control circuit for use with aglobal positioning system (GPS), or a small computer system interfacecontroller.

[0035] The microprocessor MPU on the mother board MBD is connectedillustratively to six semiconductor memories via an external bus E-BUS.These memories may be a ROM, a burst ROM (BROM), an SRAM, a PSRAM(pseudo RAM), a DRAM (dynamic RAM) and an SDRAM (synchronous DRAM). Theexternal bus E-BUS is further connected to PC card buffers BUF1 andBUF2, a display controller LCDC, and a keyboard controller KBDC. The PCcard buffers BUF1 and BUF2 are connected respectively to the PC cardslots PCSL1 and PCSL2, i.e., to the memory card MEMC and I/O card IOC.The display controller LCDC and keyboard controller KBDC are coupledrespectively to the connectors LCDCON and KBDCON, i.e., to the liquidcrystal display LCD and keyboard KBD. The semiconductor memories, the PCcard buffers and the controllers mounted on the mother board MBD arepowered individually by a power supply unit POWU.

[0036] The microprocessor MPU operates in steps in accordance withprograms read from the ROM or burst ROM, thereby carrying out logicoperations and controlling the components of the personal computer. ThePC card buffers BUF1 and BUF2 interface respectively to the memory cardMEMC and I/O card IOC. The display controller LCDC and keyboardcontroller KBDC control respectively the liquid crystal display LCD andkeyboard KBD coupled to the connectors LCDCON and KBDCON.

[0037] In this setup, the microprocessor MPU has a bus state controllerBSC, to be described later, capable of controlling in parallel theinterfaces to the semiconductor memories (ROM, burst ROM, SRAM, PSRAM,DRAM and synchronous DRAM) and to the PC cards (memory card MEMC and I/Ocard IOC). These memories and cards are all connected to the externalbus E-BUS. The address space of the external bus E-BUS is divided into apredetermined number of areas to which the semiconductor memories and PCcards are fixedly assigned. In such areas, the physical addresses ineffect when the I/O card functions as an I/O device are assignedindependently of the physical addresses used when the IO card acts as amemory. To provide for this arrangement, the microprocessor MPU includesa memory management unit MMU that converts an internal logical addressto a physical address applicable to the external bus. As a result, themicroprocessor MPU is free of constraints of physical addressassignments and requires fewer parts to be attached externally theretofor interface control. As such, the microprocessor MPU has varioussemiconductor memories and PC cards (memory card and I/O card) connecteddirectly and concurrently to the external bus E-BUS. Consequently themicroprocessor MPU becomes more convenient to use. When incorporated ina personal computer, the microprocessor MPU helps reduce the number ofsteps to design the computer. With its externally attached parts thusreduced in quantity, the microprocessor MPU allows the personal computeror the like to cost less to fabricate.

[0038] FIGS. 2(A), 2(B) and 2(C) are external views of the personalcomputer of FIG. 1. The computer in FIG. 2(A) is a so-callednotebook-sized personal computer with its PC card slots MSLOT (PCSL1,PCSL2) accommodating a memory card MEMC or an I/O card IOC incorporatinga file Ffile. The computer also has a keyboard KB (KBD) and liquidcrystal display DP (LCD) as I/O devices. The liquid crystal display maybe folded onto the computer body for portable use.

[0039] The computer in FIG. 2(B) is a so-called desk-top type personalcomputer equipped with a floppy disc drive FDD and a memory card MEMC oran I/O card IOC accommodated in a PC card slot, not shown. The cardincorporates a file Ffile. As its I/O devices, the desk-top typecomputer has a keyboard KB and a liquid crystal display DP. The floppydisc drive FDD has an appropriate floppy disc FD inserted therein. Inthis setup, the personal computer has two kinds of storage regions: asoftware-based storage region on the floppy disc FD, and ahardware-based storage region furnished by the file Ffile.

[0040] The computer in FIG. 2(C) is a so-called pen-portable typecomputer with two PC card slots for accommodating a memory card MEMC oran I/O card IOC, i.e., a file card Ffile CARD. As its I/O devices, thecomputer has a pressure-sensitive sheet equipped liquid crystal displayDP and an input pen PEN for inputting scribbled characters.

[0041] With these computers, the microprocessor MPU on the mother boardMBD has the interfaces for having various semiconductor memories and PCcards (memory card MEMC and I/O card IOC) interconnected directly andconcurrently, as mentioned earlier. The arrangement simplifies themother board MBD in structure as well as the personal computer thatincorporates it. Downsized and lightweight, the resulting computer iseasy to carry around, and has functions (e.g., burst function, to bedescribed later) permitting large amounts of data to be input and outputat high speeds. Such features allow the personal computer to processever-increasing data more quickly and more conveniently than everbefore.

[0042]FIG. 3 is a block diagram of the microprocessor MPU embodying theinvention and included in the personal computer of FIG. 1. FIG. 4 is asemiconductor substrate (semiconductor chip) layout view of themicroprocessor MPU in FIG. 3. The microprocessor MPU is formed by knownsemiconductor fabrication techniques on a semiconductor substratecomposed illustratively of single crystal silicon. One of the basiccomponents of the microprocessor MPU in FIG. 3 is a stored-program typecentral processing unit CPU comprising an arithmetic and logic unit ALU.The central processing unit CPU is connected via a system bus S-BUS(first internal bus) to a multiplier MULT, a memory management unit MMUand a cache memory CACHE. The memory management unit MMU is coupled withan address translation buffer TLB. Furthermore, the memory managementunit MMU and cache memory CACHE are connected to a cache bus C-BUS(second internal bus). The cache bus C-BUS is in turn connected to oneend of a bus state controller BSC.

[0043] The other end of the bus state controller BSC is connected to aperipheral bus P-BUS, as well as to the external bus E-BUS via a businterface and a bus connector, not shown. The peripheral bus P-BUS(third internal bus) is connected with such peripheral controllers as arefresh controller REFC, a direct memory access controller DMAC, a timercircuit TIM, a serial communication interface SCI, a digital-analogconverter D/A and an analog-digital converter A/D. The external busE-BUS is connected to the PC card buffers BUF1 and BUF2 foraccommodating the above-mentioned various semiconductor memories and PCcards, to the display controller LCDC and to the keyboard controllerKBDC. Furthermore, the bus state controller BSC, refresh controllerREFC, direct memory access controller DMAC, timer circuit TIM, serialcommunication interface SCI, digital-analog converter D/A andanalog-digital converter A/D are connected to an interrupt controllerINTC. In turn, the interrupt controller INTC is coupled to the centralprocessing unit CPU by use of an interrupt request signal IRQ.

[0044] Although not shown in FIG. 3, the system bus S-BUS, cache busC-BUS and peripheral bus P-BUS are each assumed to include an internaladdress bus for address signal transmission, an internal data bus fordata transmission, and an internal control bus for control signaltransmission. The external bus E-BUS is assumed to include an externaladdress bus for address signal transmission, an external data bus fordata transmission, and an external control bus for control signaltransmission.

[0045] The central processing unit CPU operates in synchronism with apredetermined system clock signal from a clock pulse generator CPG.Acting in this manner, the central processing unit CPU performsappropriate operations in accordance with the control program read fromthe cache memory CACHE, and controls and supervises the components ofthe microprocessor MPU. At this point, the arithmetic and logic unit ALUcarries out predetermined arithmetic and logic operations, while themultiplier MULT executes multiply or product-sum operations effectiveillustratively for digital signal processing. Upon access to memory, thememory management unit MMU converts to the corresponding physicaladdress the logical address output from inside the microprocessor MPU,i.e., from the central processing unit CPU, by referring to the addresstranslation buffer (address translation look-aside buffer) TLB. Afteraddress translation, the physical address is transmitted via the busstate controller BSC to outside of the microprocessor MPU, i.e., ontothe external bus E-BUS. The cache memory CACHE is made up of asemiconductor memory that may be accessed at high speed. The controlprogram or data is read in units of predetermined blocks from theexternal ROM or burst ROM and retained in the cache memory CACHE toprovide for the high-speed operation of the central processing unit CPU.

[0046] Meanwhile, the bus state controller BSC controls and supervisesthe operation of the various peripheral controllers as they gain accessto the peripheral bus P-BUS connected to them. The bus state controllerBSC also controls and supervises the operation of the semiconductormemories and PC cards connected to the external bus E-BUS, as well asthe operation of I/O controllers.

[0047] In this setup, the physical address space of the external busE-BUS is divided illustratively into eight areas. Seven out of the eightareas are assigned fixedly and in a predetermined combination to thesemiconductor memories and PC cards. The bus state controller BSC has afunction to control and manage parallelly the timings of the controlsignals toward the semiconductor memories and PC cards assigned to theareas of the external bus E-BUS. Various control registers are includedin the bus state controller BSC to designate the conditions for thetimings selectively. As a result, the semiconductor memories includingthe ROM, burst ROM, SRAM PSRAM, DRAM and synchronous DRAM, as well asthe PC cards including the memory card MEMC and I/O card IOC, areconnected directly and concurrently to the external bus E-BUS. Thecomposition of the signals applicable to the external bus E-BUS and aspecific constitution of the bus state controller BSC will be describedlater in more detail.

[0048] The refresh controller REFC, one of the peripheral controllers,controls the refresh operation of the DRAM and SRAM connected to theexternal bus E-BUS. The direct memory access controller DMAC supportshigh-speed data transfer illustratively between the ROM or burst ROMcoupled to the external bus E-BUS on the one hand, and the cache memoryCACHE on the other. The timer circuit TIM supports time managementnecessary for the central processing unit CPU. The serial communicationinterface SCI supports serial data transfer between the microprocessorand an external communication controller. The analog-digital converterA/D converts the analog signal from an external sensor or the like intothe corresponding digital signal. Conversely, the digital-analogconverter D/A converts the digital signal from the central processingunit CPU into the corresponding analog signal for output to the outside.

[0049] The interrupt controller INTC accepts interrupt requests from thebus state controller BSC and peripheral controllers one by one and in apredetermined order of priority. Having accepted a specific interruptrequest, the interrupt controller INTC transmits accordingly aninterrupt request signal IRQ to the central processing unit CPU.

[0050] In this setup, the components constituting the microprocessor MPUare laid out on a single semiconductor substrate subject to certainlayout conditions, as shown in FIG. 4. The components of themicroprocessor MPU are each formed as a module. That is, desired modulesare selected and combined effectively into a microprocessor according tothe user's specifications. In FIG. 4, the bus controller modulecorresponds to the bus state controller BSC and the timer modulerepresents the timer circuit TIM. The system clock signal generated bythe clock pulse generator CPG is distributed to the necessary parts ofthe microprocessor MPU via a clock driver (DRIVER in FIG. 4.).

[0051]FIG. 5 is an address map showing how the address space of theexternal bus E-BUS is divided for the microprocessor MPU of FIG. 3. FIG.6 is a partial address map showing address space areas 5 and 6 of theexternal bus in which physical addresses are illustratively assigned. InFIG. 5, the physical address space of the external bus E-BUS for themicroprocessor MPU is divided illustratively into eight areas 0 through7. Areas 0 through 6 are for use by the semiconductor memories and PCcards connected to the external bus E-BUS. Area 0 is assignedselectively to an ordinary memory, to be explained later, including theSRAM and ROM or to the burst ROM. Areas 1 and 4 are assigned selectivelyto the ordinary memory. Area 2 is assigned selectively to the ordinarymemory, SDRAM or DRAM. Area 3 is assigned selectively to the ordinarymemory, SDRAM, DRAM or PSRAM. Area 5 is assigned selectively to theordinary memory, burst ROM or memory card MEMC. Area 6 is assignedselectively to the ordinary memory, burst ROM, memory card MEMC or I/Ocard IOC. In this specification, the ordinary memory refers to theso-called address non-multiplex type memory such as the SRAM and ROMaccessed by having a row address and a column address suppliedsimultaneously, as opposed to the address multiplex type memory such asthe DRAM and SDRAM accessed by having a row address and a column addresssupplied on a time division basis.

[0052] Area 7 is assigned the addresses of the components inside themicroprocessor MPU, e.g., addresses of the internal registers of the CPUand those of the registers in the peripheral controllers. As such, area7 is not to be used by any external device. Which semiconductor memoryor PC card is to be connected to which of areas 0 through 6 isdesignated selectively by a bus control register BCR1, to be describedlater, of the bus state controller BSC.

[0053] In this setup, the system bus S-BUS, cache bus C-BUS andperipheral bus P-BUS of the microprocessor MPU have each an internaladdress bus comprising signal lines capable of transmitting 32-bitaddress signals A0 through A31. The logical addresses inside themicroprocessor MPU constitute a 4 GB (gigabyte) address space, thelogical addresses being designated alternatively by the address signalsA0 through A31. The physical addresses for outside of the microprocessorMPU, i.e., for the external bus E-BUS, are designated alternatively by29-bit address signals A0 through A28 which are short of threehigh-order bits. The three high-order bits, found in the address signalsA0 through A31, are A26 trough A28 making up address signals forgenerating chip select signals −CS0 through −CS6 by which to designateareas 0 through 6 alternatively. Low-order 26 bits, A0 through A25,constitute an address signal for designating alternatively the addressin each area. That is, the external address bus in the external busE-BUS comprises signal lines capable of transferring the address signalsA0 through A25.

[0054] As a result, area 0 is assigned physical addresses H′00000000through H′03FFFFFF (H′ stands for hexadecimal notation), and area 1 isassigned physical addresses H′04000000 through H′07FFFFFF. Areas 2, 3and 4 are respectively assigned physical addresses H′08000000 throughH′0BFFFFFF, H′0C000000 through H′0FFFFFFF, and H′10000000 throughH′13FFFFFF. Areas 5 and 6 are respectively assigned physical addressesH′14000000 through H′17FFFFFF and H′18000000 through H′1BFFFFFF. Theaddress assignments allow each area to possess a physical address spaceof 64 MB (megabytes). Adding H′20000000×n (n=1-6) to each of thephysical addresses in areas 0 through 6 provides a shadow space of eacharea. The multiplier n is designated selectively by high-order threebits of the logical address, i.e., by the address signals A29 throughA31.

[0055] The physical addresses of areas 5 and 6 assigned to the memorycard MEMC and I/O card IOC are further divided into two regions in eacharea, as shown in FIG. 6. In area 5, the low-order region of addressesH′14000000 through H′15FFFFFF is allocated as a common memory orattribute memory for use by the memory card MEMC, while the high-orderregion of addresses H′16000000 through H′17FFFFFF is inhibited from use.In area 6, the low-order region of addresses H′18000000 throughH′19FFFFFF is allocated as a common memory or attribute memory used whenthe memory card MEMC or I/O card IOC acts as a memory, whereas thehigh-order region of addresses H′1A000000 through H′1BFFFFFF serves asan I/O region used when the IO card IOC functions as an I/O device.Consequently, the common memory or attribute memory in areas 5 and 6constitutes a 32-MB address space each.

[0056] Illustratively, one of the two regions in area 6 is designatedselectively by an address signal A25 for use with the I/O card IOCfunctioning as a memory or as an I/O device. The 32-MB address space isdesignated alternatively by an address signals of the remaining 25 bits,A0 through A24. As is known in the art, the PCMCIA standards permit thePC card to have an address space of up to 64 MB. In that case, the mostsignificant bit address signal A25 is also output over a separatechannel via an output port of the microprocessor MPU, as will bediscussed later. Because the physical address space of area 6 is dividedinto two regions so that either region may be selected by the addressA25, the I/O card IOC connected to area 6 is switched dynamically byprogram execution to one of two functions: as a memory or as an I/Odevice. This feature enhances the availability of the microprocessorMPU.

[0057] As described, the physical address space of the microprocessorMPU is divided into eight areas, and seven out of the eight areas areassigned fixedly to the semiconductor memories and PC cards connected tothe external bus E-BUS of the microprocessor MPU. From the user's pointof view, this arrangement may appear to impose constraints on thesoftware-based allocation of logical addresses. However, themicroprocessor MPU of the invention incorporates the memory managementunit MMU whose internal logical addresses corresponding to the physicaladdresses of the external bus E-BUS are readily altered by updating theaddress translation buffer TLB. Specifically, the address translationtable TLB held in an external memory (e.g., DRAM) connected to theexternal bus E-BUS contains logical-physical address correspondencepairs that are easily updated as needed to alter the desired logicaladdresses. This feature frees the user from the constraints of physicaladdresses applicable to the external bus E-BUS, whereby a program havinga freely designed logical address space is written as desired.

[0058]FIGS. 7 and 8 are connection diagrams showing typical connectionsof the external bus to the microprocessor MPU of FIG. 3. FIG. 9 is aninterface block diagram of an interface example in which a PC card isconnected to the external bus E-BUS shown in FIGS. 7 and 8. FIGS. 10 and11 are tables of typical signals used on the external bus shown FIGS. 7and 8. Although FIGS. 7 and 8 show the semiconductor memories to beassigned to areas 0 through 4 more or less arbitrarily, the combinationof the memories is sometimes limited in practice depending on the area.FIGS. 10 and 11 should be referred to as needed while the arrangementsin FIGS. 7 through 9 are discussed below.

[0059] In FIG. 7, the external bus E-BUS has a 26-bit external addressbus EBA0-EBA25 and a 32-bit external data bus EBD0-EBD31 functioning asan address output bus and an I/O bus, respectively, from the point ofview of the microprocessor MPU. The address bus EBA0-EBA25 transmits theaddress signals A0 through A25 commonly to all areas to which thesemiconductor memories and PC cards are connected. The external data busEBD0-EBD31 is connected selectively depending on the bus size of thesemiconductor memories and PC cards coupled to the external bus E-BUS.The address input terminals of the DRAM and SDRAM are connected to apredetermined number of signal lines in the external address busEBA0-EBA25, because the row and column addresses to the memory are fedto the same lines within the address bus on a time division basis.

[0060] The microprocessor MPU embodying the invention uses a bus controlregister BCR2, to be described later, of the bus state controller BSC todesignate the bus size for each of areas 0 through 6. For area 0, anyone of the byte size (8 bits), word size (16 bits) and long word size(32 bits) may be selected as the bus size. For each of areas 1 through6, the byte, word or long word size may be selected if the area inquestion is assigned to the SRAM, ROM or burst ROM; if the area isassigned to the SDRAM, DRAM or PSRAM, then either the word or the longword size is selected as the bus size in combination with a memorycontrol register MCR1. Where areas 2 and 3 are assigned to the DRAM, theselectable bus size is the word size only. If areas 5 and 6 are assignedto the PC card, either the byte or the word size is selected as the bussize.

[0061] In the manner described, the low-order 16-bit data bus lines EBD0through EBD15 are connected to all semiconductor memories and PC cardsassigned to areas 0 through 6. High-order 16-bit data bus lines EBD16through EBD23 and EBD24 through EBD31 are connected selectivelydepending on the bus size for each area. Eight-bit data bus lines EBD16through EBD23 may also be used as general-purpose ports PORT0 throughPORT7 on condition that the bus size for the area in question is to be16 bits or less, as will be explained later. In this case, a portfunction enable bit of the bus state controller BSC2 is set to a logical1.

[0062] The external bus E-BUS comprises, as an external control bus EBC,control signal lines for transmitting a bus start signal −BS indicatingthat the data on the external bus E-BUS is valid (a hyphen (−) prefixedto a signal name denotes hereunder that the signal is an inverted signalthat is selectively brought Low when made valid). The signal −BS isconverted by the bus state controller BSC into start signals required bythe semiconductor memories and PC cards. For this reason, the bus startsignal −BS is supplied to the I/O controllers having bus managementfunctions such as the display controller LCDC and keyboard controllerKBDC, but not to the semiconductor memories and PC cards having no busmanagement functions.

[0063] The external control bus EBC of the external bus E-BUS includestwo kinds of control signal lines: control signal lines for transmittingthe chip select signals −CS0 through −CS6 by which to designate areas 0through 6 alternatively, and control signal lines for transmitting modesignals MD3 through MD5 by which to designate the bus size and endian ofarea 0. The chip select signals −CS5 and −CS6 double respectively ascard enable signals −CE1A and −CE1B corresponding to the PC cardsconnected to areas 5 and 6. The mode signals MD3 and MD4 double as cardenable signals −CE2A and CE2B for these PC cards. The mode signal MD5doubles as a row address strobe signal −RAS2 corresponding to asecond-set DRAM connected to area 3.

[0064] The external control bus EBC of the external bus E-BUS hasanother three kinds of control signal lines: control signal lines fortransmitting a row address strobe signal −RAS providing a start controlsignal to each of the semiconductor memories and PC cards; controlsignal lines for transmitting column address strobe signals −CASLL,−CASLH, −CASHL and −CASHH; and control signal lines for transmittingwrite enable signals −WE0 through −WE3, a read/write status signalRD/−WR, a read control signal −RD, an I/O clock signal CKIO, and a clockenable signal CKE. The I/O clock signal CKIO represents a system clocksignal input to the microprocessor MPU or an operation clock signal fedto an SDRAM if that memory is connected. Given the I/O clock signalCKIO, the microprocessor MPU controls the timings of various I/Osignals.

[0065] The row address strobe signal −RAS, supplied as such to the DRAMand SDRAM, doubles as a chip enable signal −CE toward the PSRAMconnected to area 3. The column address strobe signals −CASLL, −CASLH,−CASHL and −CASHH are supplied as such to a 32-bit bus size DRAM overdata bus lines D0-D7, D8-D15, D16-D23 and D24-D31, respectively. Ofthese column address strobe signals, the signal −CASLL doubles as acolumn address strobe signal −CAS to the SDRAM or as an output enablesignal −OE to the PSRAM. The column address strobe signals −CASEL and−CASHH double as byte-based column address strobe signals −CAS2L and−CAS2H to the second-set DRAM.

[0066] The write enable signals −WE0 through −WE3 are supplied to the32-bit bus size SRAM and PSRAM or SDRAM as write enable signals or datacontrol signals DQMLL, DQMLU, DQMUL and DQMUU corresponding to data buslines EBD0-EBD7, EBD8-EBD15, EBD16-EBD23, and EBD24-EBD31, respectively.The write enable signal −WE2 doubles as an I/O read control signal−ICIORD to the I/O card IOC connected to area 6. The write enable signal−WE3 doubles as an I/O write control signal ICIOWR. The read/writestatus signal RD/−WR is supplied as a write enable signal −WE to theDRAM and SDRAM, and doubles as a read/write signal R/−W to an I/Ocontroller, not shown. The read control signal −RD is supplied as anoutput enable signal −OE to the ROM and SRAM as well as to the memorycard MEMC and I/O card IOC. The I/O clock signal CKIO and clock enablesignal CKE are fed to the SDRAM.

[0067] In this setup, the external bus E-BUS has another two kinds ofcontrol signal lines: control signal lines working as external input buslines dedicated to PC card used to transmit a write protect signal WP;and control signal lines for transmitting a wait control signal WAIT,bus request signal −BREQ, and a bus acknowledge signal BACK for buscontrol. Of these signals, the write protect signal WP is inputselectively from a memory card MEMC that needs to be protected againstwrite operations. The write protect signal WP also doubles as a 16-bitI/O port signal −IOIS16 notifying the microprocessor MPU that the bussize of the I/O card IOC is 16 bits. The wait control signal −WAIT isselectively input as needed from a PC card or an I/O controllerrequiring the microprocessor MPU to wait in cycles. The bus requestsignal −BREQ is selectively input as needed from a bus master that wantsto monopolize the external bus E-BUS. The bus acknowledge signal BACK isoutput by the microprocessor MPU as a bus use enable signal to the busmaster. The write enable signal −WE1 output by the microprocessor MPU issent to the PC cards as a write enable signal −WE/−PGM. It should benoted that none of the semiconductor memories and PC cards shown in FIG.8 functions as a bus master.

[0068] There are also provided (not included in the external bus E-BUS)two more sets of signal lines connected to the memory card MEMC and I/Ocard IOC. One set of signal lines supplies the PC card slots PCSL1 andPCSL2 respectively with card detection signals −CD1 and −CD2 eachindicating the installation of a PC card in the slot in question. Theother set of signal lines transmits a reset signal RESET. These controlsignals are detected by a board controller BC attached to the motherboard MBD for board control purposes. The mother board MBD also hasterminals for receiving a grounding potential GND and a supply voltageVCC used as an operating power supply. The supply voltage and groundingpotential are distributed via a pair of power supply lines to thesemiconductor memories, PC cards and I/O controllers as well as to themicroprocessor MPU.

[0069] The PC cards such as the memory card MEMC and I/O card IOC areconnected to the external bus E-BUS via the PC card buffers BUF1 andBUF2, as mentioned above. The address signal A25 is furnished todetermine whether the I/O card IOC connected to area 6 is to function asa memory or as an I/O device. Thus if the memory card MEMC and I/O cardIOC have a 64-MB address space, the address signal A25 is again outputvia a port unit PORT of the microprocessor MPU in order to select thehighest-order address, as shown in FIG. 9. The port unit PORT alsohandles the reset signal RESET and an attribute memory space selectionsignal −REG. The mother board MBD includes an encoder unit ENCODER forsetting interrupt levels IRL0 through IRL3. Needless to say, thesesignals are all based on the PCMCIA standards. As depicted in FIG. 9,the PC card buffer BUF1 or BUF2 includes a bidirectional buffer B1connected to the external data bus lines EBD0 through EBD7 and abidirectional buffer B2 attached to the external data bus lines EBD8through EBD15. The data transmission direction (DIR) for each of thebidirectional buffers B1 and B2 is controlled by the read/write statussignal RD/−WR. The gating operation (G) of each of the bidirectionalbuffers B1 and B2 is controlled by the card enable signals −CE1B and−CE2B.

[0070]FIG. 12 is a block diagram of the bus state controller BSCincluded in the microprocessor MPU of FIG. 3. In FIG. 12, the bus statecontroller BSC has a cache bus interface CBIF connected to the cache busC-BUS of the microprocessor MPU. Also included in the bus statecontroller BSC are an address register ADR, a data register DTR, waitcontrol registers WCR1 and WCR2, bus control registers BCR1 and BCR2, amemory control register MCR, a DRAM control register DCR, a PCMCIAcontrol register PCR, a refresh counter register RFCR, a refresh timercount register RTCNT, a refresh time constant register RTCOR, and arefresh timer control status register RTCSR, all connected to the cachebus interface CBIF via a module bus M-BUS in the bus state controllerBSC. The contents of these registers are updated as desired by thecentral processing unit CPU of the microprocessor MPU, i.e., by theprograms contained therein. Specifically, the central processing unitCPU writes data to, and changes the contents in, each of the registers(ADR, DTR, WCR1, WCR2, BCR1, BCR2, MCR, DCR, PCMCIA, PCR, RFCR, RTCNT,RTCOR and RTCSR) by way of the cache bus C-BUS, cache bus interface CBIFand module bus M-BUS. The clock driver DRIVER supplies the bus statecontroller BSC with the operation clock signal CK generated by the clockpulse generator CPG shown in FIG. 4, the clock signal CK being used todetermine the operation timings of the bus state controller BSC. Theclock signal CK has the same frequency as that of the operation clocksignal for the central processing unit CPU, and is output as the systemclock signal through the system clock I/O terminal CKIO to outside ofthe microprocessor MPU. As will be described later, the system clocksignal output from the system clock I/O terminal CKIO is used as theoperation clock signal of the synchronous DRAM.

[0071] The address register is connected to an address controller ADC.The output terminal of the data register DTR is connected to one inputterminal of a multiplexer MPX. The other input terminal of themultiplexer MPX is connected to the ports PORT0 through PORT7. The waitcontrol registers WCR1 and WCR2 are connected to a wait controllerWATEC. The bus control register BCR1 is coupled to an area controllerAREAC. The bus control register BCR2, memory control register MCR, DRAMcontrol register DCR and PCMCIA control register PCR are connected to amemory timing controller MTC. The refresh count register RFCR, refreshtimer count register RTCNT, refresh time constant register RTCOR andrefresh timer control status register RTCSR are coupled to the refreshcontroller RFC.

[0072] The output terminal of the address controller ADC is connected tothe address bus lines EBA0 through EBA25 of the external bus E-BUS, andthe output terminal of the multiplexer MPX are connected to the data buslines EBD0 through EBD31. The output signal of the wait controller WATECbecomes the wait control signal −WAIT, and the output signal of the areacontroller AREAC turns into the chip select signals −CS0 through −CS6and card enable signals −CE2A and −CE2B. The output signals of thememory timing controller MTC are: the bus start signal −BS, row addressstrobe signal −RAS doubling as chip enable signal −CE, column addressstrobe signal −CAS/−CASxx (the suffix “xx” generically representshereunder variations of, say, the column address strobe signal such as−CASLL, −CASLH, −CASHL and −CASHH), write enable signal −WEx doubling asdata control signal DQMxx, I/O read control signal −ICIORD doubling asI/O write control signal −ICIOWR, read/write status signal RD/−WR, readcontrol signal −RD, write protect signal WP doubling as 16-bit I/O portsignal −IOIS16, and clock enable signal CKE.

[0073] The address controller ADC transmits the address signals A0through A25 coming from the address bus of the cache bus C-BUS to theaddress bus lines EBA0 through EBA25 of the external bus E-BUS.Furthermore, the address controller ADC has an address generatingfunction to update automatically certain bits of the address signals inburst mode in which a series of addresses are accessed consecutively.The multiplexer MPX connects the cache bus C-BUS with the data bus linesEBD0 through EBD31 of the external bus E-BUS. Where certain bits of thedata bus (i.e., data bus lines EBD16 through EBD23) are used as theports PORT0 through PORT7, the multiplexer MPX performs the switchingbetween data bus function and port function. As outlined, the bus statecontroller BSC incorporates the address controller ADC having theaddress generating function for use in burst mode. Thus thesemiconductor memories and PC cards having burst mode are connected tothe microprocessor with no increase in the number of parts to beexternally attached to the latter, and the memories and cards may beaccessed consecutively at high speed.

[0074] The wait controller WATEC supplies the microprocessor MPU with acycle wait request sent from a PC card or an I/O controller using thewait signal −WAIT over the external bus-E-BUS. On the basis of theconstants written in the wait control registers WCR1 and WCR2, the waitcontroller WATEC selectively executes the insertion of idle cycles uponswitching from read to write access or the insertion of a wait state foreach of the areas.

[0075] The area controller AREAC selectively generates the chip selectsignals −CS0 through −CS6 and card enable signals −CE2A and CE2B inaccordance with the assignment attributes written in the bus statecontrol register BSC1 regarding areas 0 through 6 and on the basis ofthe area selection signal fed via the address bus lines A26 through A28of the cache bus C-BUS. The memory timing controller MTC selectivelygenerates under predetermined timing conditions the start controlsignals needed to control the operation of the semiconductor memoriesand PC cards. The selective generation of the start control signals iscarried out on the basis of the bus size attributes written in the buscontrol register BCR2 regarding areas 0 through 6 and in accordance withthe constants written in the memory control register MCR, DRAM controlregister DCR and PCMCIA control register PCR. The refresh controller RFCcontrols the refresh operation on the DRAM, SDRAM, etc., by making useof an overflow interrupt function of the refresh counter.

[0076]FIG. 13 indicates a state transition diagram applicable to the busstate controller BSC of FIG. 12. FIG. 14 is a table indicating typicalstates applicable to the states of the bus state controller BSC shown inFIG. 13. FIG. 15 is a table of typical transition conditions for the busstate controller BSC of FIG. 13. FIG. 16 shows typical signal waveformsin effect when the memory card MEMC is accessed by the microprocessorMPU of FIG. 3 not entailing wait state, FIG. 17 shows typical signalwaveforms in effect when the memory card MEMC is accessed by themicroprocessor MPU entailing wait state, and FIG. 18 shows typicalsignal waveforms in effect when the memory card MEMC is accessed by themicroprocessor MPU in burst mode. FIG. 19 illustrates typical signalwaveforms in effect when the I/O card IOC is accessed by themicroprocessor MPU not entailing wait state, and FIG. 20 depicts typicalsignal waveforms in effect when the I/O card IOC is accessed by themicroprocessor MPU entailing wait state. In a detailed description thatfollows regarding the state transition of the bus state controller BSCas outlined in FIG. 13, the reader is asked to refer to FIGS. 14 through20 where necessary. The states shown in FIGS. 13 through 15 are only apart of the states for control over the SRAM, burst ROM and PC cards.The bus state controller BSC has many other states regarding control ofother semiconductor memories. FIGS. 16 through 20 include for referencethe I/O clock signal CKIO, bus start signal −BS and read/write statussignal RD/−WR which are not supplied to the memory card MEMC and I/Ocard IOC. The I/O clock signal CKIO used as the system clock or as theoperation clock signal of the central processing unit CPU serves as thebasic clock signal by which to generate diverse timing signals shown inFIGS. 16 through 20.

[0077] In FIG. 13, the bus state controller BSC of this embodiment actsas a so-called state machine having 10 states ST1 through ST10 forcontrol over the SRAM, burst ROM, memory card MEMC and I/O card IOC. Ofthese states, state ST1 is an idle state corresponding to the wait stateof the microprocessor MPU, as shown in FIG. 14. States ST2, ST3 and ST4denote a PCMCIA TED1 state, a PCMCIA TED2 state and a PCMCIA TED3 state,respectively. The three states are used to delay by one cycle the timeto set up the address signals A0 through A25 for the write enable signal−WE1 and output enable signal −OE serving as the start control signalsof the PCMCIA, i.e., the memory card MEMC and I/O card IOC. States ST5,ST6 and ST7 represent respectively a NORM T1 state corresponding to anaccess start cycle, a NORM TW state corresponding to a wait cycle, and aNORM T2 state corresponding to an access end cycle. States ST8, ST9 andST10 denote respectively a PCMCIA TEH1 state, a PCMCIA TEH2 state and aPCMCIA TEH3 state, each being used to delay by one cycle the time tohold the address signals A0 through A25 for the write enable signal −WE1and output enable signal −OE. States ST1 through ST10, listed to matchthe cycle names in the “Corresponding Cycle” column in FIG. 14, arekeyed to the corresponding cycles that are illustrated in FIGS. 16through 20.

[0078] Suppose that transition condition No. 1 in FIG. 15 is met withthe bus state controller BSC in state ST1 (i.e., idle state). This meansthat the external bus E-BUS is free; that a request for access to amemory, i.e., to the external bus E-BUS has occurred; and that theconstant TED set in the PCMCIA control register PCR regarding the delayof the setup time is 1, 2 or 3. In that case, the bus state controllerBSC enters state ST2 wherein a delay cycle for the time to set up thewrite enable signal −WE1 and output enable signal −OE is initiated. Atthis point, in the memory card MEMC and I/O card IOC, a Tpcm0 cycle or aTpci0 cycle is used to delay by one cycle of the I/O clock signal CKIOthe time to set up the bus start signal −BS, i.e., write enable signal−WE1 and output enable signal −OE (read control signal −RD), as shown inFIGS. 17 and 20.

[0079] Suppose now that transition condition No. 4 in FIG. 15 is met.This means that the one-cycle delay of the setup time in state ST2 hasended and that the constant TED in the PCMCIA control register PCR is 2or 3. In that case, the bus state controller BSC enters stateST3.wherein a delay cycle for the time to set up the write enable signal−WE1 and output enable signal −OE is again initiated. At this point, inthe memory card MEMC and I/O card IOC, a Tpcm0w cycle or a Tpci0w cycleis used to delay by another cycle of the I/O clock signal CKIO the timeto set up the bus start signal −BS, i.e., write enable signal −WE1 andoutput enable signal −OE, as shown in FIGS. 17 and 20.

[0080] Suppose now that transition condition No. 3 in FIG. 15 is met.This means that the one-cycle delay of the setup time in state ST3 hasended and that the constant TED in the PCMCIA control register PCR is 2.In that case, the bus state controller BSC enters state ST5 wherein anaccess start cycle is initiated. At this point, in the memory card MEMCand I/O card IOC, a Tpcm1 cycle or a Tpci1 cycle is used to get the busstart signal −BS, i.e., output enable signal −OE (I/O read controlsignal −ICIORD) or write enable signal −WE1 (I/O write control signal−ICIOWR) driven Low to the valid level, as shown in FIGS. 17 and 20.This effectively triggers data write or read operations to or from theaddresses designated by the address signals A0 through A25.

[0081] Suppose that transition condition No. 2 is met in which theone-cycle delay of the setup time in state ST2 has ended and in whichthe constant TED in the PCMCIA control register PCR is 1. In that case,the bus state controller enters state ST5 wherein an access start cycleis initiated. If transition condition No. 5 is met in which theone-cycle delay of the setup time in state ST3 has ended and in whichthe constant TED in the PCMCIA control register PCR is 3, then the busstate controller BSC enters state ST4. In this state, the time to set upthe write enable signal −WE1 and output enable signal −OE is delayed byanother cycle. When transition condition N. 6 is met in which theone-cycle delay of the setup time in step ST4 has ended, state ST5 isreached.

[0082] Suppose now that transition condition No. 7 is met with the busstate controller BSC in state ST1 (i.e., idle state). This means thatthe external bus E-BUS is free, that a request for access to a memoryhas occurred, and that the constant TED in the PCMCIA control registerPCR is 0. In that case, the bus state controller BSC directly entersstate ST5 wherein an access start cycle is initiated. At this point, inthe memory card MEMC and I/O card IOC, a Tpcm1 cycle or a Tpci1 cycle isexecuted without the intervention of a cycle for delaying the time toset up the write enable signal −WE1 and output enable signal −OE, asshown in FIGS. 16 and 19. This permits access to the target memory forwriting or reading data thereto or therefrom.

[0083] Suppose that transition condition No. 9 is met in which theaccess start cycle in state ST5 has ended and in which the constant WAITin the wait control register WCR2 is illustratively 1. In that case, thebus state controller BSC enters state ST6 wherein a wait cycle isinitiated. At this point, in the memory card MEMC and I/O card IOC, onewait state made up of two Tpcm1w or Tpci1w cycles is inserted in orderto delay driving High the output enable signal −OE (I/O read controlsignal ICIORD) or write enable signal −WE1 (I/O write control signal−ICIOWR), i.e., to delay the end of the data write or read operation, asshown in FIGS. 17 and 20. During the delay, the wait control signal−WAIT is brought Low in a time period encompassing the next leading edgeof the I/O clock signal CKIO that occurs, and is driven back in a timeperiod comprising the subsequent leading edge of the signal CKIO.

[0084] When transition condition No. 12 is met in which the wait cyclein state ST6 has ended, the bus state controller BSC enters state ST7wherein an access end cycle is initiated. At this point, in the memorycard MEMC and I/O card IOC, a Tpcm2 or Tpci2 cycle is used to drive backHigh the output enable signal −OE (I/O read control signal −ICIORD) orwrite enable signal −WE1 (I/O write control signal −ICIOWR) to theinvalid level, as shown in FIGS. 16 through 20. This terminates the datawrite or read operation to or from the designated address. Suppose thattransition condition No. 10 is met with the bus state controller BSC instate ST6. This means that the constant WAIT in the wait controlregister WCR2 is other than 2 and that the wait state needs to remain ineffect. In that case, the bus state controller BSC inserts another waitcycle using state ST6.

[0085] When the access end cycle based on state ST7 has ended, the busstate controller BSC goes selectively to state ST1, ST2, ST5 or ST6depending on the ending state of burst mode or all cycles and on theconstants TED and TEH in the PCMCIA control register PCR, i.e., thedelay conditions for the setup time and hold time. That is, iftransition condition No. 12 is met in which burst mode has yet to beended during the access end cycle of state ST7, the bus state controllerBSC returns to state ST6. The process is repeated until burst mode ends.At this point, in the memory card MEMC and I/O card IOC, as many busstart signals −BS and output enable signals −OE as the number of burstsare generated intermittently, as shown in FIG. 18. Concurrently, theaddress controller ADC of the bus state controller BSC successivelygenerates the low-order four-bit address signals A0 through A3 toperform consecutive access to a series of addresses.

[0086] Meanwhile, suppose that transition condition No. 13 is met. Thismeans that the access end cycle based on state ST7 has ended, that allcycles of byte- or word-based divided access operations effected becauseof a limited bus size have yet to be ended, and that the setup time andhold time need not be delayed. In that case, the bus state controllerBSC returns to state ST5 and repeats the access operation. At thispoint, suppose that transition condition No. 14 is met in which thesetup time needs to be delayed. This causes the bus state controller BSCto enter state ST2. If transition condition No. 16 or 18 is met in whichthe hold time needs to be delayed, the bus state controller BSC goes tostate ST8, ST9 or ST10 depending on the number of the delay cyclesneeded.

[0087] The burst mode for the memory card MEMC and I/O card IOC inconnection with areas 5 and 6 is furnished so as to implement 16-byteaccess operations to a cache file in the same manner as in the page modeof a burst ROM. In this case, the number of data transfer operations inburst mode may be set using the bus control register BCR1. The number ofconsecutive access operations may be selected from three options: 4, 8or 16 times. In the first access cycle of burst mode for reading data,the data designated by the read request is accessed; in the remainingcycles, the 16-byte boundary data including the data in question isaccessed in wrap around fashion. In burst mode for writing data, 16-byteboundary data is written consecutively to the region corresponding tothe data, starting from the first address of that region. The number ofwait states inserted during the first access and from the second accessonward is set selectively using the constant WAIT in the wait controlregister WCR2, as mentioned above.

[0088] When transition condition No. 15 is met in which all cycles areconfirmed ended in the access end cycle of state ST7 and in which thehold time need not be delayed, the bus state controller BSC returns tostate ST1. At this point, suppose that transition condition No. 16, 17or 18 is met. This means that the constant TEH in the PCMCIA controlregister PCR is at least 1 and that the hold time needs to be delayed.In that case, the bus state controller BSC goes selectively to stateST8, ST9 or ST10 depending on the number of delay cycles involved, i.e.,according to the value of the constant TEE in the PCMCIA controlregister PCR.

[0089] Suppose that the bus state controller BSC enters a delay cycle instate ST8 after transition condition No. 16 has been met. In thatcase,-in the memory card MEMC and I/O card IOC, a Tpcm2w or a Tpci2wcycle is inserted in order to delay by one cycle the hold timebetween-the rise of the output enable signal −OE (I/O read controlsignal −ICIORD) or write enable signal −WE1 (I/O write control signal−ICIOWR) and the next transition of the address signals A0 through A25,as shown in FIGS. 17 and 20. When the bus state controller BSC enters adelay cycle of state ST9 after transition condition No. 17 has been met,two Tpcm2w or Tpci2w cycles are inserted so as to delay by two cyclesthe hold time in question. If the bus state controller BSC enters adelay cycle of state ST9 after transition condition No. 18 has been met,three Tpcm2w or Tpci2w cycles are inserted to delay the hold time bythree cycles.

[0090] At the end of the delay cycle in state ST8, the same endingcondition as in state ST7 is selected. The bus state controller BSC goesselectively to state ST1, ST2 or ST5 depending on the ending state ofall cycles and in accordance with the constant TED in the PCMCIA controlregister PCR, i.e., according to the delay condition for the setup time.That is, if transition condition No. 22 is met in which all cycles haveyet to be ended at the end of the delay cycle in state ST8 and in whichthe setup time need not be delayed, the bus state controller BSC returnsto state ST5; if transition condition No. 21 is met in which the setuptime needs to be delayed, the bus state controller BSC returns to stateST2. The access is then repeated in each case. When transition conditionNo. 23 is met in which all cycles are confirmed ended in state ST8, thebus state controller BSC returns to state ST1 (idle state).

[0091] In the manner described, the bus state controller BSC havingcomplex functions to deal with various semiconductor memories and PCcards may be used as a state machine whose transition conditions are setselectively by updating the constants in the control registers. Thisarrangement makes it possible to align efficiently the interfaceconditions for areas 0 through 6 of the external bus E-PUS with those ofthe semiconductor memories and PC cards connected to these areas. At thesame time, the logic structure of the bus state controller BSC issimplified while the flexibility of the controller as it constitutespart of the system is enhanced.

[0092]FIG. 21 is an interface block diagram of a connection example inwhich synchronous DRAMs and a PC card (MEMC/(IOC)) are connected to themicroprocessor MPU of this invention. Since how the PC card (MEMC/(IOC))and the microprocessor MPU are interconnected was discussed earlier indetail with reference to FIG. 9, FIG. 21 shows only a part of theconnections involved, and the description of the connections in FIG. 21will be omitted where redundant.

[0093] As shown in FIG. 21, an SDRAM1 and an SDRAM2 have a memorystructure of 256 K×16 bits each. The SDRAM1 comprises: address terminalsA9 through A0 connected to receive address signals A11 through A2 outputby the microprocessor MPU; a clock terminal CKL connected to the systemclock I/O terminal CKIO of the microprocessor MPU; a clock enable signalterminal CKE connected to the clock enable signal terminal CKE of themicroprocessor MPU; a chip select signal terminal −CS connected to thechip select signal terminal −CS3 of the microprocessor MPU; a rowaddress strobe signal −RAS connected to the row address strobe signalterminal −RAS/−CE of the microprocessor MPU; a column address strobesignal terminal −CAS connected to the column address strobe signalterminal −CAS/−OE of the microprocessor MPU; a write enable signalterminal −WE connected to the read/write status signal terminal RD/−WRof the microprocessor MPU; data I/O terminals I/O15 through I/O0connected respectively to the data I/O terminals D31 through D16 of themicroprocessor MPU; and data control signal terminals DQMU and DQMLconnected respectively to the data control signal terminals DQMUU andDQMUL of the microprocessor MPU.

[0094] The SDRAM2 includes: address terminals A9 through A0 connected toreceive address signals A11 through A2 output by the microprocessor MPU;a clock terminal CKL connected to the system clock I/O terminal CKIO ofthe microprocessor MPU; a clock enable signal terminal CKE connected tothe clock enable signal terminal CKE of the microprocessor MPU; a chipselect signal terminal −CS connected to the chip select signal terminal−CS3 of the microprocessor MPU; a row address strobe signal −RASconnected to the row address strobe signal terminal −RAS/−CE of themicroprocessor MPU; a column-address strobe signal terminal −CASconnected to the column address strobe signal terminal −CAS/−OE of themicroprocessor MPU; a write enable signal terminal −WE connected to theread/write status signal terminal RD/−WR of the microprocessor MPU; dataI/O terminals I/O15 through I/O0 connected respectively to the data I/Oterminals D15 through D0 of the microprocessor MPU; and data controlsignal terminals DQMU and DQML connected respectively to the datacontrol signal terminals DQMLU and DQMLL of the microprocessor MPU.

[0095] Where the microprocessor MPU is connected as shown in FIG. 21with the synchronous DRAMs (SDRAM1, SDRAM2) offering high-speed addressaccess time, the synchronous DRAMs may be utilized as a 32-bit-widememory in the setup. The system clock signal output from the systemclock I/O terminal CKIO of the microprocessor MPU is a clock signalhaving the same frequency as that of the operation clock signal of thecentral processing unit CPU. The system clock signal is also fed to thebus state controller BSC.

[0096]FIG. 22 illustrates bus cycle waveforms which are used to explainhereunder the burst read operation of the synchronous DRAM (SDRAM1,SDRAM2). Although omitted from FIG. 22, the clock enable signal CKE isassumed to be held High. When the synchronous DRAM is refreshed, theclock enable signal CKE is brought Low selectively. The bus start signal−BS is a strobe signal for monitoring the bus cycles and is notconnected to the synchronous DRAM.

[0097] In the first cycle Tr, the signal −CS3 corresponding to the spacearea to which the synchronous DRAM is assigned is driven Low, and therow address strobe signal −RAS is also brought Low. This causes theappropriate row address to be moved into the synchronous DRAM. In thenext cycle Tc, the column address strobe signal −CAS is driven Low,causing the appropriate column address to be taken into the synchronousDRAM. In this manner, the appropriate signals (−CS2, −RAS, −CAS andaddress signals output in synchronism with a leading edge of the clocksignal CKIO from the CPU) are brought into the synchronous DRAM insynchronism with a leading edge of the clock signal CKIO. That is, theread operation and other operations, not shown, on the synchronous DRAMare controlled on the basis of the clock signal CKIO.

[0098] In the third cycle Td1, the signal −CAS is reset and driven High.Over four cycles starting from the third cycle (Td1-Td4), data D31through D0 are read consecutively from the synchronous DRAM. Such aburst read operation allows 16 bytes of data (4 bytes×4 cycles) to beread out. The control signals based on the above-described timings aregenerated by the bus state controller BSC.

[0099]FIG. 23 is a block diagram of a typical synchronous DRAM (simplycalled SDRAM). The kind of SDRAM shown in FIG. 23 is formed, but notlimited, by known semiconductor integrated circuit fabricationtechniques on a single semiconductor substrate composed illustrativelyof single crystal silicon.

[0100] The SDRAM of FIG. 23 comprises a memory array 200A constituting amemory bank A (BANKA) and a memory array 200B making up a memory bank B(BANKB). The memory arrays 200A and 200B are each made up of dynamicmemory cells arranged in matrix fashion. Referring to FIG. 23, aselection terminal for memory cells constituting a single column isconnected to a word line (not shown) coupled to the column in question.A data I/O terminal for memory cells forming a single row is connectedto a complementary data line (not shown) coupled to the row in question.

[0101] One of the word lines, not shown, of the memory array 200A isdriven to the selection level in accordance with the output of a rowdecoder 201A having decoded a row address signal. The complementary datalines, not shown, of the memory array 200A are connected to a senseamplifier and column selector circuit 202A. A sense amplifier in thesense amplifier and column selector circuit 202A is an amplifier circuitthat detects and amplifies a small potential difference that appears onindividual complementary data lines in the event of a data readoperation on memory cells. A column switching circuit in the senseamplifier and column selector circuit 202A is a switching circuit thatselects any one of the complementary data lines for conduction to acomplementary common data line 204. The column switching circuitsfunction selectively in accordance with the output of a column decoder203A having decoded a column address signal. A row decoder 201B, a senseamplifier and column selector circuit 202B, and a column decoder 203Bare likewise furnished on the side of the memory array 200B. Thecomplementary common data line 204 is connected to the output terminalof an input buffer 210 and to the input terminal of an output buffer211. The input terminal of the input buffer 210 and the output terminalof the output buffer 211 are connected to the 16-bit data I/O terminalsI/O0 through I/O15.

[0102] The column and row addresses supplied from the address inputterminals A0 through A9 are brought into a column address buffer 205 anda row address buffer 206 on an address multiplex basis. The suppliedaddress signals are retained in the respective buffers. In refreshoperation mode, the row address buffer 206 receives as a row address therefresh address signal from a refresh counter 208. The output of thecolumn address buffer 205 is sent as preset data to a column addresscounter 207. In the operation mode designated illustratively by acommand, the column address counter 207 outputs to the column decoder203A or 203B the column address signal received as preset data or acolumn address signal having been incremented successively.

[0103] A controller 212 is connected to, but not limited by, an inputterminal CLK for receiving the clock signal CKIO, an input terminal forreceiving the clock enable signal CKE, an input terminal for receivingthe chip select signal −CS, an input terminal for receiving the columnaddress strobe signal −CAS, an input terminal for receiving the rowaddress strobe signal −RAS, an input terminal for receiving the writeenable signal −WE, and input terminals for receiving data controlsignals DQMU and DQML. The controller 212 is supplied with externalcontrol signals via the above-described input terminals and with controldata through the address input terminals A0 through A9. On the basis ofthe level changes in these signals and according to the timings thereof,the controller 212 generates internal timing signals by which to controlthe operation mode of the SDRAM and the operation of the circuit blocksoutlined above. When acting in this fashion, the controller 212 utilizescontrol logic circuits, not shown, and a mode register 30 incorporatedtherein.

[0104] The clock signal CKIO is regarded as the master clock of theSDRAM. The other externally input signals are made significant insynchronism with leading edges of the clock signal CKIO. The chip selectsignal −CS designates the start of a command input cycle when drivenLow. The chip select signal −CS has no meaning when brought High(representing a chip nonselected state) or in other input states. Itshould be noted that the memory bank selection state and such internaloperations as a burst operation are not affected by the transition tothe chip nonselected state. The signals −RAS, −CAS and −WE differ infunction from the corresponding signals for the ordinary DRAM; they aremade significant only when command cycles are defined.

[0105] The row address signal is defined by the levels of the terminalsA0 through A8 in a row address strobe bank active command cyclesynchronized with a leading edge of the clock signal CKIO. In the rowaddress strobe bank active command cycle, the input from the terminal A0is regarded as a bank selection signal. Specifically, when the inputfrom the terminal A9 is Low, the memory bank BANKA is selected: when theinput from the terminal A9 is High, the memory bank BANKB is selected.Memory bank selection is controlled, but not limited, by such processesas activation of the row decoder alone on the side of the selectedmemory bank, nonselection of all column switching circuits on the sideof the nonselected memory bank, and connection of only the selectedmemory bank to the input buffers 210 and 211. The input from theterminal A8 in a pre-charge command cycle designates how pre-charging isto be carried out on complementary data lines. When the input from theterminal A8 is High, both memory banks are designated to be pre-charged;when the input from the terminal A8 is Low, one memory bank designatedby the input from the terminal A9 is to be pre-charged. The columnaddress signal is defined by the levels of the terminals A0 through A7in a read or write command (column address read command or columnaddress write command) cycle synchronized with a leading edge of theclock signal CKIO. The column address thus defined is regarded as thestart address for a burst access operation.

[0106] As described, the operation of the synchronous DRAM is controlledon the basis of the clock signal CKIO. The memory card MEMC and I/O cardIOC furnished as PC cards are also controlled in accordance with theclock signal CKIO, as is understood from the preceding description ofhow the bus state controller BSC operates. It follows that where the PCcards (memory card MEMC, I/O card IOC) are controlled in operation whilethe synchronous DRAM is running at high speed, it may happen that therequired time to set up the output enable signal −OE or write enablesignal −WE as a PC card start signal with regard to the decay of theclock signal CKIO or to the address signals fails to meet thecorresponding PC card standards. In such cases, as is understood fromthe description above of how the bus state controller BSC works withreference to FIGS. 17 and 20, the bus state controller BSC utilizes thePCMCIA control register PCR furnished therein. On the basis of theconstant TED regarding the setup delay or the constant TEH regarding thehold delay in the PCMCIA control register PCR, the bus state controllerBSC controls the time to set up or hold the output enable signal −OE orwrite enable signal −WE as the PC card start signal with regard to thedecay of the clock signal CKIO or to the address signals.

[0107] The arrangement above thus controls the time to set up the outputenable signal −OE or write enable signal −WE as the PC card start signalwith regard to the delay of the clock signal CKIO or to the addresssignals. This makes it possible for the microprocessor MPU of theinvention to gain access to the PC cards and synchronous DRAMs with noproblem even where these cards and memories are connected concurrentlyto the microprocessor MPU.

[0108] The effects offered by the embodiment above are summarized below.

[0109] (1) The microprocessor to be incorporated in personal computersand the like is equipped with the bus state controller which isconnected to the external bus of the microprocessor and which controlsparallelly the interfaces of various semiconductor memories (ROM, burstROM, SRAM, PSRAM, DRAM and synchronous DRAM) and PC cards (memory cardand I/O card). Constituted as described, the inventive microprocessorreduces the number of externally attached parts for interface controlwhile allowing the semiconductor memories and PC cards to be connecteddirectly and concurrently to the external bus of the microprocessor.

[0110] (2) With the embodiment structured as summarized in paragraph (1)above, the address space of the external bus is divided into apredetermined number of areas to which the semiconductor memories and PCcards are fixedly assigned. The microprocessor also includes the memorymanagement unit for converting an internal logical address to thecorresponding physical address applicable to the external bus. Thisarrangement frees the user from the constraints of physical addressesregarding the external bus E-BUS, and makes it possible to write aprogram having a freely designed logical address space.

[0111] (3) With the embodiment structured as summarized in paragraphs(1) and (2) above, the physical address space assigned to the I/O cardis further divided into two portions. That is, the physical addressesfor the I/O card acting as a memory are assigned separately from thosefor the I/O card functioning as an I/O device. The address space areasthus furnished are designated selectively using specific bits in theaddress signal. In this manner, the I/O card is switched dynamicallybetween the memory function and the I/O device function on a softwarebasis.

[0112] (4) With the embodiment structured as summarized in paragraphs(1) through (3) above, the bus state controller is regarded as a statemachine. This bus state controller comprises control registers wherebythe types and the operating conditions of the semiconductor memories andPC cards assigned to the various areas are readily set on a softwarebasis. This makes it possible to align efficiently the interfaceconditions for each of the areas with those of the semiconductormemories and PC cards. At the same time, the logic structure of the busstate controller is simplified while the flexibility of the controlleras it constitutes part of the system is enhanced.

[0113] (5) With the embodiment structured as summarized in paragraphs(1) through (4) above, the bus state controller is equipped with thefunction to generate addresses in burst mode. This makes it possible toconnect the semiconductor memories and PC cards having burst mode to themicroprocessor without increasing the number of externally attachedparts of the microprocessor while boosting the speed of access to thememories and cards.

[0114] (6) With the advantages summarized in paragraphs (1) through (5)above, the inventive microprocessor is easy and convenient to use. Whenincorporated in a personal computer having the PC card interface, themicroprocessor helps reduce the number of steps to design the computer.With its externally attached parts thus reduced in quantity, themicroprocessor allows the personal computer or the like to cost less tofabricate.

[0115] Although the description above contains many specificities, theseshould not be construed as limiting the scope of the invention but asmerely providing illustrations of the presently preferred embodiments.It is evident that many alternatives, modifications and variations willbecome apparent to those skilled in the art in light of the foregoingdescription. For example, in FIG. 1, the types, quantities andcombination of the semiconductor memories and PC cards connected to theexternal bus E-BUS of the microprocessor MPU (i.e., mother board MBD)may be varied as needed. The personal computer may have various I/Odevices and may take any one of diverse block constitutions andconnection forms With reference to FIGS. 2(A) through 2(C), the personalcomputer may take any one of other external appearances. In FIG. 3, themicroprocessor MPU may take any other block constitution and bus makeup.The basic layout of the microprocessor MPU shown in FIG. 4 is but one ofmany other possible layouts and is not limitative of the invention.

[0116] With reference to FIGS. 5 and 6, the physical address space ofthe external bus E-BUS may be divided into any number of areas to whichsemiconductor memories and/or PC cards may be assigned as desired. Theexamples in FIGS. 7 through 11 do not limit the invention in terms ofthe signal composition for the external bus E-BUS, the valid levels andfunctions of the signals used, and the combination of semiconductormemories and PC cards.

[0117] Referring to FIG. 12, the block constitution of the bus statecontroller BSC including the types and combination of the registers usedmay be varied as needed. In FIGS. 13 through 15 regarding the bus statecontroller BSC acting as a state machine, the logic constitution and thefunctions and transition conditions for various states may vary. Theexamples in FIGS. 16 through 20 are not limitative of the invention interms of the logic levels of and temporal relations between the addresssignals and start control signals in various access modes.

[0118] The foregoing description has centered primarily on themicroprocessor constituting part of the personal computer, which is thebackground technical field of the inventors. However, this particularbackground of the inventors is not limitative of the invention; theinvention may also be applied to microprocessor used in various otherportable data terminals and computers. The invention is appliedextensively to microprocessors comprising at least an external bus andto devices or systems comprising such a microprocessor.

[0119] To sum up, the major benefits available with the invention are asfollows: the microprocessor for use in personal computers and portabledata terminals has the bus state controller which is connected to theexternal bus and which controls parallelly the interfaces of varioussemiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM andsynchronous DRAM) and PC cards (memory card and I/O card). Themicroprocessor of this constitution reduces the number of externallyattached parts for interface control while allowing the semiconductormemories and PC cards to be connected directly and concurrently to themicroprocessor.

[0120] The address space of the external bus of the microprocessor isdivided into a predetermined number of areas to which the semiconductormemories and PC cards are fixedly assigned. The microprocessor alsoincludes the memory management unit for converting an internal logicaladdress to the corresponding physical address applicable to the externalbus. The setup frees the user from the constraints of physical addressesregarding the external bus, and makes it possible to write a programhaving a freely designed logical address space.

[0121] The physical address space assigned to the I/O card is furtherdivided into two portions. In this case, the physical addresses for theI/O card acting as a memory are assigned separately from those for theI/O card functioning as an I/O device. The address space areas thusfurnished are designated selectively using specific bits in the addresssignal. The setup allows the I/O card to be switched dynamically betweenthe memory function and the I/O device function on a software basis.

[0122] The bus state controller is regarded as a state machine, andincludes control registers whereby the types and the operatingconditions of the semiconductor memories and PC cards assigned to thevarious areas are readily set on a software basis. The setup alignsefficiently the interface conditions for each area with those of thesemiconductor memories and PC cards. At the same time, the logicstructure of the bus state controller is simplified while theflexibility of the controller as it constitutes part of the system isenhanced.

[0123] The bus state controller has the function to generate addressesfor consecutive access to a series of addresses in burst mode. Thisconnects the semiconductor memories and PC cards having burst mode tothe microprocessor without increasing the number of externally attachedparts of the microprocessor while boosting the speed of access to thememories and cards.

[0124] Offering the advantages above, the microprocessor is easy andconvenient to use. When incorporated in a personal computer having thePC card interface, the microprocessor helps reduce the number of stepsto design the computer. With its externally attached parts thus reducedin quantity, the microprocessor allows the personal computer or the liketo cost less to fabricate.

What is claimed is:
 1. A microprocessor comprising an interface circuitfor permitting semiconductor memories and PC cards to be connecteddirectly to said microprocessor.
 2. A microprocessor according to claim1, wherein said interface circuit generates a plurality of controlsignals to be output onto an external bus of said microprocessor;wherein said semiconductor memories include a ROM, a burst ROM, an SRAM,a PSRAM, a DRAM and a synchronous DRAM; and wherein said PC cardsinclude a memory card and an I/O card.
 3. A microprocessor according toclaim 2, wherein said external bus has an address space divided into aplurality of areas assigned fixedly to predetermined semiconductormemories and PC cards, said microprocessor further comprising a memorymanagement unit for converting an internal logical address to a physicaladdress applicable to said external bus.
 4. A microprocessor accordingto claim 3, wherein said external bus is capable of having at least partof said semiconductor-memories connected concurrently with said memorycard and said I/O card to said microprocessor.
 5. A microprocessoraccording to claim 4, wherein said I/O card functions either as an I/Odevice or a memory, and wherein the physical addresses in effect whensaid I/O card acts as the I/O device are assigned independently of thosein effect when said I/O card functions as the memory.
 6. Amicroprocessor according to claim 3, further comprising a bus statecontroller including registers for inter-face control between saidsemiconductor memories and said PC cards, said registers being used toset the types and the operating conditions of said semiconductormemories and said PC cards assigned to said areas.
 7. A microprocessoraccording to claim 6, wherein at least part of said semiconductormemories and said PC cards have burst mode for consecutive access to aseries of addresses, and wherein said bus state controller has anaddress generating circuit for use in said burst mode.
 8. Amicroprocessor according to claim 7, wherein said bus state controlleris a state machine.